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全球嵌入式系統研發領域之軟體領導者 IAR正式發表其旗艦產品的重大更新版本：Arm 開發工具 v9.70 和 RISC-V 開發工具 v3.40。現代化工具鏈大幅提升了 IAR 開發平台在性能、安全性和自動化方面的能力，協助汽車、工業、醫療和物聯網等產業更高效地因應複雜的系統開發挑戰，加速產品上市。 為因應嵌入式系統日益提升的複雜度，全新 IAR 開發工具支援雲端與本地部署、彈性的授權機制、CI/CD 整合以及多種架構的開發支援。隨著 Arm 和 RISC-V 持續推動技術發展，IAR 透過統一的平台提供高品質且具安全保障的開發體驗。新版本協助客戶提升研發效率、降低開發成本、加快產品上市步調，使嵌入式系統開發更具可預測性和可擴充性。 IAR 產品長 Thomas Andersson 表示：「IAR 始終致力於打造為 Arm 與 RISC-V 創新設計的工具鏈，協助客戶實現技術突破與差異化競爭。此次產品升級不僅加強了 IAR 嵌入式開發平台的整體能力，更進一步優化了與 DevOps 的整合，實現跨架構程式碼複用，並內建安全合規開發支援，所有功能均可透過彈性的雲端訂閱模式取得，為客戶帶來更高的自由度。」 新版本進一步強化對現代 DevOps 實踐與分散式開發流程的支援，提升了對開源 SDK 的相容性，並新增對基於 CMake 的建構流程和外部生成可執行檔的支援，協助開發團隊在本地環境或容器化 CI/CD 中高效協作，確保開發流程一致性與可追溯性。 在功能方面，Arm 開發工具同時新增對 GNU C/C++ 和 C++20 的擴充支援，進一步簡化與開源工具和晶片廠商 SDK 的整合流程; RISC-V開發工具則擴充了對 DSP 和 SIMD 指令集的支援，並相容汽車級 IP（如 Synopsys ARC-V），使開發者能更安心地應用針對產業的高可靠性解決方案。 透過將現代開發流程整合至單一平台，IAR 有效解決了工具鏈碎片化問題。 IAR嵌入式開發平台全面支援 ISO 26262、IEC 61508 和 IEC 62304 等安全標準，協助開發人員加速認證流程、保護智慧財產權、縮短產品上市時間，同時便於維護現有專案，並在處理器生態持續發展的背景下保障技術連續性，為開發團隊賦能，以實現更快、更彈性和更可靠的工作模式。 此外，IAR 最新發表的 Visual Studio Code 擴充 v1.42 為開發平台也帶來了先進的 RTOS 感知除錯能力。開發人員可以在熟悉的開發環境中深入洞察系統運作狀態，包括任務和中斷日誌、多核心執行視圖，以及對 Arm 平台上 Zephyr RTOS 的原生支援。相關加強功能可有效提升開發效率、簡化除錯流程，並顯著強化對複雜嵌入式系統的可視性。 憑藉以上多項創新，IAR 平台將協助開發團隊加快反覆運算週期、提升程式碼品質、優化資源利用，全面提升交付效率與開發投報率。 欲了解更多關於IAR嵌入式開發平台資訊，請瀏覽：https://www.iar.com/embedded-development-tools 關於IAR IAR處於為嵌入式開發提供全球領先之軟體和服務的最前端，使全球公司能推出形塑未來的安全和突破性產品。自1983年成立以來，IAR的解決方案在確保品質、安全、可靠性和效率方面發揮了重要價值，為包括汽車、工業自動化、物聯網、醫療科技、軍事及公共安全等眾多產業開發了超過一百萬個嵌入式應用。憑藉對來自超過70個半導體合作夥伴之15,000種裝置之支援，IAR致力於促進創新及協助客戶獲致成功。IAR總部位於瑞典烏普薩拉（Uppsala），並於世界各地策略性地設立業務和支援辦公室，為I.A.R. Systems Group AB子公司，並於納斯達克OMX斯德哥爾摩交易所上市，屬中型股指數（ticker symbol: IAR B）。更多資訊請瀏覽www.iar.com
SAN JOSE, Calif. and HYDERABAD, India, June 12, 2025 /PRNewswire/ -- Cyient Semiconductors Private Limited, a fast-growing custom silicon company based in Hyderabad, and MIPS, a global leader in RISC-V processor IP, today announced a strategic collaboration to develop domain-optimized ASIC (application-specific integrated circuit) and ASSP (application-specific standard product) solutions that leverage the MIPS Atlas portfolio of advanced, efficient processor IP. The partnership will focus on enabling real-time, safety-critical applications, power delivery, and compute efficiency in demanding platforms for automotive, industrial, and data center markets. Motor Control & Data Center Power Delivery are focal platforms to leverage Cyient's Analog Mixed Signal capabilities and MIPS Atlas CPU IP. "As compute systems scale from cloud to the edge, intelligent power delivery is emerging as a key enabler of performance and efficiency," said Suman Narayan, CEO of Cyient Semiconductors. "Our collaboration with MIPS allows us to bring together embedded intelligence and advanced power architectures in custom silicon platforms built on a scalable, open foundation. Together, we are designing tomorrow's semiconductors — purpose-built for a more connected and power-efficient world." "The problem of power efficiency and motor control are both real-time compute workloads for which MIPS M8500 microcontrollers are the optimal choice," said Sameer Wasson, CEO of MIPS. "Building around our best-in-class real-time and control-loop performance and efficiency, Cyient can bring their unique capability in intelligent power delivery into custom ASIC and ASSP designs to build differentiated solutions that meet our customers unique needs in their target markets." Demand for software defined vehicles, data center infrastructure, and industrial automation is driving growth for custom silicon. Customers can build advanced, differentiated solutions that are easy to program using MIPS advanced processor IP, based on the open RISC-V instruction set architecture, combined with Cyient intelligent power and mixed-signal design expertise. Targeted applications include motor drive control, intelligent power management, power delivery management, and safety-critical applications, offered as ASSP or ASIC platforms. OEMs and system integrators will benefit from faster time-to-market, avoiding proprietary lock-ins, and optimized platform cost. About MIPS MIPS is the leading provider of compute subsystems for autonomous platforms in automotive, industrial, and embedded markets. With a 40-year heritage in RISC computing innovation and safety capable processing, MIPS is uniquely positioned to simplify the adoption of Physical AI in industrial robotics and automotive applications. MIPS pioneering patented technology is based on the open specification RISC-V instruction set architecture, enabling customers to move beyond proprietary legacy architecture lock-ins. For more information, please visit MIPS.com. About Cyient Semiconductor Cyient Semiconductors, a Cyient Group company, delivers high-performance, power-efficient silicon solutions across analog, mixed-signal, RF, and digital domains. Serving HPC, data centres, industrial automation, communications, automotive, and healthcare sectors, it supports the full chip lifecycle—from architecture to production—through both turnkey and design service models. The company works closely with leading semiconductor firms, OEMs, Tier-1s, and global partners across fabrication, OSAT, and IP to enable scalable, future-ready silicon innovation. Gowtham Uyalla Kaizzen PR gowtham.uyalla@kaizzencomm.com press@mips.com Phalguna Hari jandhyala Cyient Phalguna.Harijandhyala@cyient.com
SAN JOSE, Calif., April 23, 2025 /PRNewswire/ -- S2C, a global leader in FPGA-based prototyping solutions, and Andes Technology, a premier provider of high-performance, low-power RISC-V processor IP solutions, today announced the results of a strategic collaboration designed to significantly enhance FPGA prototyping capabilities for developers of advanced System-on-Chip (SoC) devices. The partnership leverages S2C's new Prodigy™ S8-100 FPGA prototyping platform, based on the AMD Versal™ Premium VP1902 adaptive SoC, to deliver unprecedented capacity and flexibility for modeling, prototyping, and software development using Andes' cutting-edge RISC-V cores.Historically, FPGA prototyping faced capacity limitations, restricting SoC developers' ability to integrate multiple RISC-V cores along with subsystems like Network-on-Chip (NoC), DDR, PCIe® controllers, and more. The Prodigy S8-100 platform addresses these challenges by offering a single FPGA version with up to 100 million logic gates – providing ample capacity for Andes' most advanced RISC-V processors, including the customers' differentiating extensions enabled by the Andes' Automated Custom Extension (ACE) framework, and additional IPs.The Prodigy S8-100 family also includes larger configurations with two or even four VP1902 adaptive SoCs, scaling capacity up to 400 million logic gates per system. This substantial increase in logic capacity enables full SoC validation in hardware, significantly reducing development cycles, optimizing performance modeling, and accelerating software development before production silicon becomes available. Moreover, the platform supports S2C's extensive library of nearly 100 daughter cards to support applications ranging from networking, storage, and multimedia to generic IOs facilitating efficient interface modeling and simulation without sacrificing FPGA logic resources."The collaboration between S2C and Andes marks a significant step forward for the RISC-V community, offering advanced SoC developers a powerful and cost-effective FPGA-based prototyping solution," said Ying J Chen, Vice President of S2C. "Our Prodigy S8-100 platform uniquely addresses the evolving complexity of RISC-V-based designs, helping developers validate their innovations early and confidently accelerate time-to-market."Emerson Hsiao, President of Andes Technology USA, stated: "Andes continues to drive innovation in high-performance RISC-V cores tailored to AI, automotive, and high-performance computing, and many of our customers further differentiate by adding their own extensions with our ACE framework. Partnering with S2C provides our customers with the critical advantage of robust, large-capacity FPGA-based prototyping, allowing them to prove-out their customizations early, ultimately accelerating their time-to-market with Andes-based RISC-V SoCs." "Designed for emulation and prototyping, the AMD Versal Premium VP1902 adaptive SoC is uniquely positioned to address cutting-edge development challenges," said Mike Rather, senior product line manager, AMD. "As the industry's largest FPGA-based adaptive SoC, the Versal VP1902 adaptive SoC empowers engineers to push the boundaries of technology, offering high performance, scalability, and connectivity in a single device. With its advanced emulation and prototyping capabilities, it is a catalyst for groundbreaking innovations in next-generation semiconductor innovation." Live Demonstration at Andes RISC-V ConThe S2C Prodigy S8-100 system will be demonstrated live at the Andes RISC-V Con, themed "RePioneering the Future," on April 29, 2025, at the DoubleTree by Hilton Hotel in San Jose. Attendees are invited to visit the S2C booth to experience firsthand the advanced FPGA-based prototyping capabilities that will drive the next wave of RISC-V-based innovation.To learn more about the Andes RISC-V Con event, please visit the registration site.About S2CS2C is a global leader in FPGA prototyping solutions, providing scalable, reliable, and flexible hardware platforms that accelerate system validation and software development for semiconductor companies worldwide. For more information, visit www.s2cinc.com.About Andes TechnologyAs a Founding Premier member of RISC-V International and a leader in commercial CPU IP, Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is driving the global adoption of RISC-V. Andes' extensive RISC-V Processor IP portfolio spans from ultra-efficient 32-bit CPUs to high-performance 64-bit Out-of-Order multiprocessor coherent clusters. With advanced vector processing, DSP capabilities, the powerful Andes Automated Custom Extension (ACE) framework, end-to-end AI hardware/software stack, ISO 26262 certification with full compliance, and a robust software ecosystem, Andes unlocks the full potential of RISC-V, empowering customers to accelerate innovation across AI, automotive, communications, consumer electronics, data centers, and mobile devices. Over 16 billion Andes-powered SoCs are driving innovations globally. Discover more at www.andestech.com and connect with Andes on LinkedIn, X, Bilibili and YouTube AMD, Versal, and combinations thereof are registered trademarks of Advance Micro Devices, Inc.
智慧系統的發展早已超越傳統硬體升級，轉向系統整合、運算架構與感測技術的全方位演進。近期從蔚來 ET9 搭載高解析智慧車燈、Microchip 進軍車用 SoC FPGA、到安森美（onsemi）推出高性能 iToF 感測器，顯示 AI、車用與光電感測的跨界融合，正逐步重塑智慧應用的疆界。 蔚來 ET9 搭載 25,600 像素智慧車燈 重新定義車與環境互動 蔚來最新旗艦車款 ET9，成為全球首批搭載艾邁斯歐司朗 EVIYOS™ HD 25 多像素 LED 晶片的量產車型。EVIYOS HD 25 搭載高達 25,600 顆可獨立控制的微型 LED，可主動在夜間投影行車路線、行人提示與風險警示資訊，具備 500 公尺遠距照明能力與地面光毯功能，將車燈從傳統照明裝置轉變為智慧駕駛輔助平台。 觀點解析：車燈不再只是亮度與數量的競爭，而是演算法、感測模組與光源技術融合的實力展現。EVIYOS 模組化設計預示著車燈將成為車與環境即時互動的重要節點。 Microchip 推 PolarFire SoC FPGA 推動 RISC-V 進軍車用核心 Microchip 宣布其 PolarFire® SoC FPGA 通過 AEC-Q100 車規認證，正式進入車用 SoC 應用領域。該晶片具備 -40°C 至 125°C 工作溫度範圍，支援 Linux 與 RTOS 作業系統，並內建 500K 邏輯元件。結合高能效與嵌入式安全特性，適用於 ADAS、電池管理與智慧閘道器等場景。 觀點解析：RISC-V 架構逐步進入以 Arm 為主的車用運算領域，PolarFire SoC 所代表的中階密度 FPGA 架構，對追求模組化、高整合度的車用平台具備高度吸引力，為 Tier-1 車電供應商提供更多開放選項。 安森美推出 Hyperlux ID 感測系列 iToF 深度感知突破 30 公尺 為解決傳統 iToF 感測器在解析度與穩定性上的限制，安森美推出 Hyperlux™ ID 系列產品，搭載 1.2MP 全域快門感測器，實現最遠 30 公尺的即時深度感測能力，並優化移動目標偵測與戶外運作表現。應用場景涵蓋工業自動化、AR/VR、智慧安防與自駕技術。 觀點解析：iToF 感測的競爭不再侷限於硬體規格，而是平台整合能力的比拼。安森美透過整合雷射板、演算法支援與開發套件，將 3D 感測推向更廣泛且實用的應用層面。 小結：AI 車用應用融合加速，技術邊界持續擴張 三項來自不同領域的創新突破，皆指向未來智慧應用的共同趨勢： 光電整合：EVIYOS 模組結合 LED、演算法與µ-driver，讓車燈成為資訊顯示與互動載體。 運算架構開放化：RISC-V FPGA 跨入車用主控市場，推動開放平台設計。 3D 感測普及化：iToF 精準度與範圍大幅提升，為工業與自駕應用創造更大落地空間。 從車頭到晶片核心，智慧應用的融合戰爭正如火如荼展開，無論是在自駕車、智慧工廠還是未來機器人技術中，這些突破將加速新世代智慧系統的實現。 參考來源： 蔚來車燈新聞：https://www.ezpr.com.tw/蔚來et9搭載艾邁斯歐司朗智能多像素led產品eviyos-hd-25/ Microchip 車規認證：https://www.ezpr.com.tw/microchip-polarfire-soc-fpga通過aec-q100汽車級認證/ 安森美 iToF 感測器：https://www.ezpr.com.tw/安森美技術突破攻克itof現有挑戰/
HANGZHOU, China, Jan. 9, 2025 /PRNewswire/ -- Recently, SpacemiT, a RISC-V AI CPU company from China, announced breakthrough progress in the development of its server CPU chip SpacemiT Vital Stone® V100. It now provides a complete RISC-V CPU chip hardware and software platform that fully supports server specifications. Key IPs: RISC-V CPU core X100, AIA and APLIC supporting interrupt virtualization, IOMMU supporting memory virtualization, IOPMP supporting security functions, LPC and eSPI supporting communication with mainstream BMCs, etc. The 64-bit server-grade RISC-V CPU core X100 delivers a single-core performance of >9 points/GHz on SPECINT2006 at 2.5GHz@12nm. X100 supports the RVA23 Profile, full virtualization (Hypervisor 1.0, AIA 1.0, IOMMU), RAS features, Vector 1.0 extension, vector encryption and decryption, security, 64-core interconnect, and more. The IOMMU IP adheres to the RISC-V IOMMU architecture specification and the AXI4-Stream DTI interface, supporting configurable DID, PID, virtual address, physical address width, and various levels of translation cache sizes. It can be flexibly integrated into different locations within the SoC bus system to enable distributed peripheral virtualization and accelerator acceleration. X100 Multicore System Key Subsystems: Including CPU subsystem, bus subsystem, IOMMU subsystem, interrupt subsystem, debug & trace subsystem, clock & reset subsystem, RMU management and control subsystem, etc., thereby realizing the development of the server CPU chip platform. Software R&D Progress: Based on the self-developed server CPU chip platform, the development of server platform firmware that complies with the RISC-V BRS Spec specification has been completed. This includes openSBI/UEFI (BIOS)/Linux and other low-level software that meets the requirements of the Supervisor Binary Interface (SBI), UEFI (BIOS), SMBIOS, ACPI, and other specifications. The Linux operating system has been adapted and ported, and it supports the GlobalPlatform-standard OP-TEE secure operating system. The platform firmware and operating system can now be successfully run and demonstrated on an FPGA of the server CPU chip platform. Software About SpacemiT: SpacemiT is a computing ecosystem enterprise based on the new-generation RISC-V architecture, with a layout covering full-stack computing technologies such as high-performance RISC-V CPU cores, AI-CPU cores, AI CPU chips, and software systems. It provides end-to-end computing system solutions and is committed to building the best native computing platform for the new AI era of large models using RISC-V AI CPUs, thereby promoting the development of new applications such as AI computers and AI robots. Please visit https://www.spacemit.com/en/ for more information. Business Contactbusiness@spacemit.com Media Contactmedia@spacemit.com
聖荷西，美國加州 - Media OutReach Newswire - 2024年11月22日 - 領先的高效可配置 IP 計算核心開發商 MIPS 今天宣佈正式推出 MIPS P8700 系列 RISC-V 處理器。P8700 提供業界領先的加速計算、功率效率和可擴展性，旨在滿足 ADAS 和自動駕駛汽車 (AV) 等最先進汽車應用的低延遲、高密集數據傳輸需求。' 典型的ADAS 和自動駕駛解決方案往往依賴粗暴的提高性能方法，即以提高時鐘頻率和核心數量，強行實現困難的合成式性能。P8700 具有多執行緒和節能架構，使 MIPS 客戶能夠實現比當前市場解決方案更少的 CPU 核心和更低的熱設計功耗 (TDP)，從而使 OEM 能夠以經濟實惠且高度可擴展的方式開發 ADAS 解決方案。它還通過提供高效、最佳化且低功耗的延遲敏感解決方案(專門針對中斷負載多感測器平臺)來緩解數據行動效率低下的系統瓶頸。 對於具有 AI 自主軟體堆疊的 L2+ ADAS 系統，MIPS P8700 還可以卸載深度學習中不易量化的核心處理元素，並通過基於稀疏性的卷積處理函數來減少處理元素，從而使 AI 堆疊軟體利用率和效率提高 30% 以上。 MIPS 執行長 Sameer Wasson 表示：「汽車市場需要能夠即時處理來自多個感測器的大量數據，並以高效方式為 AI 加速器進行處理的 CPU。MIPS 多執行緒和其他針對汽車應用客製化的架構掛鉤，使其成為數據密集型處理任務的有力核心。這將使汽車 OEM 擁有高性能計算系統，消耗更少電量並更好地利用 AI 加速器。」 MIPS P8700 核心採用基於 RISC-V ISA 的多核/多叢集和多執行緒 CPU IP，目前正與多家主要 OEM 合作進行批量生產。Mobileye (納斯達克股票代碼：MBLY) 等主要客戶已採用這種方法來開發未來的自動駕駛汽車和高度自動化駕駛系統產品。 Mobileye 工程執行副總裁 Elchanan Rushinek 表示：「我們成功開發用於 ADAS 和自動駕駛汽車的 EyeQ™ 片上系統，有賴關鍵合作夥伴MIPS。MIPS P8700 RISC-V 核心的推出，將有助於我們為全球汽車製造商持續開發產品以實現更高性能以及卓越成本和功耗效率。」 P8700 系列是一款高性能亂序處理器，採用 RISC-V RV64GC 架構，包括專為提高性能、功耗、面積尺寸而設計的新 CPU 和系統級功能，以及基於傳統 MIPS 微架構所建立的其他成熟功能，目前已在全球 OEM 市場上部署了 30 多種車型。MIPS 的最新處理器旨在提供業界領先的計算密度，具有三個關鍵架構特性，包括： MIPS 亂序多執行緒 — 支援每個時鐘週期執行來自多個執行緒 (harts) 的多條指令，從而提高利用率和 CPU 效率。 一致的多核、多叢集 — P8700 系列可擴展至在一個叢集中包含 6 個一致的 P8700 核心，每個叢集都支援直接連接加速器。 功能安全 — 旨在滿足 ASIL-B(D) 功能安全標準 (ISO26262)，整合了多種故障檢測功能，例如位址和數據匯流排上的端到端同位保護、軟體可見寄存器上的同位保護、用於向系統報告故障的故障匯流排等。 MIPS P8700 處理器現已在廣泛市場推出，主要合作夥伴已經準備就緒。預計不久將通過 OEM 供貨。 有關 MIPS P8700 的更多資訊，請瀏覽 MIPS.com/markets/automotive/。 Hashtag: #MIPS發佈者對本公告的內容承擔全部責任關於 MIPSMIPS 正在加速汽車、雲端和嵌入式市場的計算密度。MIPS 業界領先的核心可配置、高效且易於實施，讓客戶能夠自由地為特定工作負載構建獨特的產品。其多執行緒方法提供了高級可擴展性以及高效行動和更快處理數據的能力。該公司的計算 DNA 跨越三十年，迄今為止已出貨數十億塊基於 MIPS 的晶片。如需瞭解更多資訊，請瀏覽 www.MIPS.com。
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